Since the advent of the first microprocessor, the exponential growth in computing power has driven a similar need for increased data communication transfer rates. For internal data communications between a computer and its memory or internal peripherals, a shared bus has been the conventional interface structure. An example of a conventional internal data bus structure is the PCI interface. The PCI bus is a high-performance successor to the original IBM PC internal peripheral bus, the ISA bus. Even with a 133 MB/s data rate, the PCI bus has been extended to keep up with the data transfer needs of more powerful processors by doubling the clock rate from 33 MHz to 66 MHz, doubling the data path width from 32 bits to 64 bits, and including multi-rate clocking and a more efficient data transfer protocol.
Despite these extensions, the parallel PCI bus may eventually be replaced by a high-speed serial link architecture called PCI EXPRESS. The PCI EXPRESS architecture uses low-voltage differential signaling, a packet-based data transmission protocol and an extendable high-speed data rate beginning at 2.5 Gb/s. A typical PCI EXPRESS implementation may use a four-wire interface to provide a bi-directional transmit signal path and receive signal path. Such an implementation would use a first pair of wires to transmit a differential signal along a unidirectional signal path for transmitting data from a transmitter on a first device to a receiver on a second device, and a second pair of wires would be used to transmit another differential signal along another unidirectional signal path for transmitting data from a transmitter on the second device to a receiver on the first device. Although more wires are required per data bit than with some conventional data buses, the PCI EXPRESS message-based protocol and embedded clocking eliminates the need for many of the data control signals required by systems that utilize such conventional data buses.
Despite the advantages of the PCI EXPRESS architecture, implementing the PCI EXPRESS protocol in a data communication system can be difficult and expensive. For example, the PCI EXPRESS protocol includes physical signaling to indicate OOB state information (e.g., Electrical Idle, Receive Detect, Beacon Signal, etc.). If the two end devices of a serial, high-speed communication link support physical OOB signaling, then one or more intermediate devices in the link (e.g., a repeater, multiplexer/demultiplexer, a router, bridge, hub or the like) may also need to support physical OOB signaling.
Additionally, the PCI EXPRESS protocol includes presence detection and loss of signal (LOS) mechanisms for detecting missing or failed terminating devices (e.g., a “missing” graphics card that has been removed from a socket at one end of the PCI EXPRESS bus). If there are one or more intermediate devices in the link between an originating device (e.g., a microprocessor or computer chipset) and a terminating device (e.g., a graphics processor, graphics card, sound card, host bus adaptor, network interface card, secondary processor or microcontroller, or other peripheral or supplemental device), then there is a possibility of false presence detection of the terminating device. In this case, the intermediate device may mask from the originating device the true connection status of the terminating device. While the originating device may be able to detect a missing or failed terminating device at a higher layer in the protocol stack (e.g., a logical layer above the physical layer), such detection may result in a loss of cycle time and power, which may be unacceptable for some applications.
Accordingly, mechanisms for bridging OOB information across a sequence of interfaces and/or for preventing false presence detection of terminating devices are desired.
Like reference numerals refer to corresponding parts throughout the drawings.